1. Field of the Invention
The present invention relates to the field of phase-locked loops and in particular to that of phase-locked loops of frequency synthesizers made in the form of integrated circuits.
2. Discussion of the Related Art
FIG. 1 schematically shows an example of a phase-locked loop of a frequency synthesizer. A quartz oscillator 1 generates a reference signal REF having a reference frequency Fref. A comparator 2 comprises a phase detector 3 receiving signal REF and a feedback signal FDBK. A charge pump 4 is coupled to the output of detector 3. Charge pump 4 generates a current Icom depending on the phase-shift between the signals received by detector 3. Current Icom is filtered and transformed into a control voltage Vcom by an RC-type filter 5. A variable-frequency oscillator 6 (VCO) controlled by control voltage Vcom generates an output signal OUT having a frequency Fout. A frequency divider 8 generates, based on signal OUT, feedback signal FDBK having a frequency equal to frequency Fout divided by a programmable integral value N. When the phase-locked loop is stabilized, the frequencies of signals Fref and FDBK are equal and one has:Fout=N.Fref
It is desirable in a frequency synthesizer to be able to accurately set frequency Fout within an extended range of values. It is further desirable for frequency Fref to be as high as possible, to reduce the size of the capacitors of filter 5 of comparator 2. Large capacitors are indeed expensive in an integrated circuit.
One prior art solution consists of periodically modifying value N according to a sigma/delta modulation pattern so that divider 8 divides in average the frequency of signal OUT by a real value ranging between value N and a value N+1. Such a modulation however introduces on feedback signal FDBK a phase error which must be corrected in comparator 2 by using in filter 5 capacitors still having a significant size. Further, such a modulation introduces an unwanted jitter in the phase-locked loop.
Another solution to increase the accuracy of the phase-locked loop consists of multiplying the frequency of output signal OUT of the loop by an accurately-programmable real value. Such a multiplication may be performed by a multiplexer receiving on a plurality of inputs a plurality of phase-shifted replicas of signal OUT. The multiplexer is controlled according to a sigma/delta modulation pattern to output from the multiplexer a signal having an average period equal to the period of signal OUT multiplied by a programmable real fractional number. The sigma/delta modulation however introduces on the multiplexer's output signal a jitter and a phase error which make such a solution impossible to use for a large number of applications.